1. Field of the Invention
The present invention relates generally to semiconductor die assemblies that employ multiple semiconductor dice. More specifically, the present invention relates to methods and apparatus for increasing integrated circuit density by employing a plurality of semiconductor dice in semiconductor assemblies utilizing single lead frames.
2. State of the Art
High performance, low cost, increased miniaturization of components, and greater packaging density of integrated circuits have long been the goals of the computer industry. Greater integrated circuit density, for a given level of active component and internal conductor density, is conventionally limited by the space available within a packaging envelope and by the surface area, or “real estate”, available on a carrier substrate such as a printed circuit board.
In addition, simplicity and reduced processing of semiconductor die assemblies are preferable. For instance, reduction of parts and processing steps reduces the cost of semiconductor components. More specifically, it is preferable to plate one side of a package lead frame because plating more than one side adds cost and processing time to lead frame production. In addition, processing complexities may preclude plating the entire lead frame.
For conventional lead frame-mounted semiconductor dice, space limitations are a result of the basic design. Conventional lead frame design inherently limits potential single-die package density because the die-attach paddle of the lead frame is usually as large as or larger than the die residing on the paddle. The larger the die, the less space (relative to size of the die) that remains around the periphery of the die-attach paddle for bond pads for wire bonding. Furthermore, the inner lead finger ends on a lead frame may provide anchor points for the leads when the leads and the die are encapsulated, as with a filled polymer by transfer molding. These anchor points may be embodied as flanges or bends or kinks in the lead finger. As the sizes of packages approach the sizes of their dice therein, there is a corresponding reduction in the available encapsulant material depth along the sides of a package for the lead fingers to anchor to the encapsulant material and for the encapsulant material to provide a robust seal about and between the lead fingers. As a consequence of this reduction of the amount of encapsulant material into which the lead fingers may be encapsulated, anchored, and sealed, the encapsulant material may crack and destroy the package integrity, substantially increasing the probability of premature device failure, as the lead fingers (after encapsulation) are subjected to the normal stresses of trimming, forming and assembly with a carrier substrate, such as a printed circuit board.
One method of increasing integrated circuit density is to stack a plurality of dice vertically. U.S. Pat. No. 5,012,323 to Farnworth teaches combining a pair of dice mounted on opposing sides of a lead frame. An upper die is back-bonded to the upper surface of the leads of the lead frame via a first adhesively coated, insulated film layer. The lower die is face-bonded to the lower lead frame die-bonding region via a second, adhesively coated, insulative, film layer. The wire-bonding pads on both the upper die and lower die are interconnected with the ends of their associated lead extensions with gold or aluminum bond wires. The lower die is slightly larger than the upper die so that the lower die bond pads are accessible from above through an aperture in the lead frame such that wire bonds can be made from these bond pads to lead extensions. However, this arrangement has a major disadvantage from a production standpoint, since differently sized dice are required. Moreover, the lead frame design employed by Farnworth is directed toward peripherally located bond pads and includes a rather complex lead frame configuration, which may not be amenable to use in standard thin small outline packages (TSOPs).
U.S. Pat. No. 5,291,061 to Ball teaches a multiple stacked die device that contains up to four dice and which does not exceed the height of then-current single die packages. The low profile of the device is achieved by close-tolerance stacking which is made possible by a low-loop-profile wire bonding operation and thin-adhesive layers between the dice of the stack. However, although Ball secures all of the dice to a single lead frame, the bond pads of each die employed are peripherally located.
U.S. Pat. No. 5,804,874 to An et al. discloses the stacking of two or more identical leads-over-chip (“LOC”) configured semiconductor dice facing in the same direction. A lower die is adhered by its active surface to leads of a lower lead frame and wire bonded in LOC fashion, after which the active surface of at least one other die is adhered to leads of an upper lead frame in LOC fashion, then adhesively back bonded to the upper surface of the lower lead frame. The leads of the upper lead frame are electrically connected to those of the lower lead frame by thermocompression bonding. The An device, while providing increased circuit density, requires at least two differently configured LOC lead frames and that bond pads of both dice be wire bonded to their corresponding leads before the at least two dice are secured together. Moreover, the asymmetrical die arrangement and coverage of the wire bonds of the lower die by the upper die may induce an irregular flow front of filled polymer encapsulant material as the assembly is encapsulated by transfer molding, resulting in incomplete encapsulation without voids and increased probability of bond wire sweep and consequent shorting.
U.S. Pat. No. 6,252,299 to Masuda et al. discloses an LOC-type semiconductor package wherein an upper die and a lower die, each with centrally located bond pads, are electrically connected to separate lead fingers of respective lead frames. In addition, the upper and lower dice are configured such that the circuit-bearing surfaces of each die are opposed to each other. Therefore, the Masuda invention employs multiple lead frames, which must be electrically isolated from one another, potentially increasing the thickness of the resulting package to an undesirable level.
U.S. Pat. No. 6,087,718, issued to Cho discloses a stacked-type semiconductor package wherein an upper die with peripherally located bond pads and a lower die with centrally located bond pads are electrically connected to a single lead frame. However, the use of differently configured semiconductor dice in Cho may be somewhat undesirable.
Thus, it would be advantageous to develop a technique and device for increasing integrated circuit density in the form of a TSOP-style semiconductor device assembly utilizing semiconductor dice with centrally located bond pads that are electrically bonded to the same surface of a single lead frame.